::CONTENTS::




	Contents VLSI - ILP :-
	1. Verilog HDL 2. VHDL 3. Digital Design 4. STA (Static Timing Analysis) 5. DFT (Design for Testability) 6. SPICE 7. MOS and Semiconductor Physics 8. Linux 9. Perl/shell Scripting 10. Digital CMOS Designing 11. HDL Simulation and Synthesis 12. Memory specific Training 13. Analog Designing with SPICE 14. Layout Designing

Verilog HDL
	Introduction to Verilog Syntax and Semantics Gate Level Modeling Verilog Behavioral Modeling Test Fixtures Behavioral Modeling of combinational Logic Behavioral Modeling of Sequential Behavioral Modeling of Memories Tasks and Functions Switch level Modeling Advanced Behavioral Modeling Concepts Modeling Component Libraries Advanced Verilog Topics

VHDL
	Introduction to VHDL VHDL Language structure Gate level Modeling Structural Modeling Behavioral Modeling Types and Attributes Subprograms and Packages Predefined Attributes Configurations Advanced topics Modeling Considerations

Digital Design
	Binary Systems Boolean algebra and logic gates Gate level Minimization Combinational logic Synchronous sequential Logic Registers and counters Asynchronous sequential logic Finite state machines (Mealy , Moore types)

STA (Static Timing Analysis)
	Timing Models Propagation delay , rise delay , fall delay Arrival time , Required time Clock frequency , clock period , duty cycle Setup and Hold time Clock skew , clock Zitter Latch , flip flop timing Clock Borrowing Divided clock , gated clock frequency calculation Slack Analysis (setup , hold) Multicycle path analysis False Path False path elimination

DFT (Design for Testability)
	i Introduction CAD tools used Logic Test - Typical Fault Models Advanced Faults Models Design for Test Logic BIST Memory Test (March Algorithm) Test Compression Fault diagnosis IEEE 1149.1 TAP Scan Testing Techniques Industrial Case Studies

SPICE
	Introduction to SPICE Syntax & Semantics of SPICE Model (Input Conventions) Simulation Concepts Simulation Commands Device Statements Device Models Capacitor , Diode , MESFET , MOSFET Level4(BSIM1) , MOSFET Levels 13 , 28 , 29 MOSFET Levels 49 , 53 (BSIM3 Revision3) , BJT , Coupled Transmission lines , JFET , Additional MOSFET Parameters Small Signal and Noise Models Diode , BJT , JFET/MESFET , MOSFET User Defined External Models External Tables

MOS & Semiconductor Physics
Energy Bands and Charge Carriers in Semiconductors Excess Carriers an Semiconductors JUNCTIONS MOS Physics (Device Level) MOS Circuit theory MOS Transistor switches. nMOS, pMOS Enhancement Device Threshold Voltage MOS Device Design Equations DC equations Second Order Effects Body Effect , Subthreshold Region ,channel Length Modulation Mobility , Drain Punch through , Impact Ionization MOS Models , Noise Margin , CMOS Inverter , CMOS Inverter as an Amplifier MOS Inverter Static Characteristics MOS Inverters : Switching Characteristics and Interconnect Effects Combinational MOS Logic Circuits Sequential MOS Logic Circuits Dynamic MOS Logic Circuits Low Power CMOS Logic Circuits Circuit Characterization and performance estimation Scaling of MOS Transistor Dimensions DSM Effects

Linux
Linux Introduction Understanding Linux Commands General Purpuse Utilities The File System Handling Ordinary Files File Attributes The vi Editor The shell The process Filters - pr , head , tail , cut , paste , sort , uniq , tr Filters Using regular expressions - grep and sed Advanced Filters shell/perl Concepts

Perl/shell
Getting Started Basic Operators and Control Flow Scalar Variables Operators List and Array Variables Reading From and Writing to files Pattern Matching Control Structures Using Subroutines Associative arrays Formatting Output Working with file systems Process, String, and Mathematical Functions Scalar-Conversion and List-Manipulation Functions System Functions Command-Line Options System Variables References in Perl Object-Oriented Programming in Perl Miscellaneous Features of Perl The Perl Debugger

Digital CMOS Designing
n Introduction Digital Circuit Design an Overview Design and performance analysis of CMOS inverter Circuit structure, VTC , Static Operation , Dynamic Operation , Dynamic Power Dissipation , Effect of Parameter variations on VTC CMOS Logic Gates Circuits Basic Structure , NOR gate , NAND gate , Combinational , Sequential , PUN and PDN network , Obtaining PUN form PDN , Synthesis Methods summery , Transistor Sizing , Pseudo-NMOS Logic Circuits Pass Transistor Logics Dynamic Logic Circuits SPICE Simulation

HDL Simulation and Synthesis
HDL Simulation and Synthesis Concepts What is Simulation Types of Simulation Simulation levels synthesis issues Goals of synthesis why synthesis Synthesis design Flow RTL descriptions Synthesis with, Without constraints synthesis characterization Levels of synthesis HDL coding styles for improved synthesis results Synthesis Advantages Timing Driven Synthesis Technology Library Redundant Logic (How to remove)

Memory Specific Training
Memory Classification Memory Design Issues Latches and Flip flops Multivibrator Circuit Memory Timing Definitions Semiconductor Memories : Types and Architecture Random Access Memory (RAM) cells SRAM (6T cell , DRAM(4T cell , 1T cell) RAM Peripheral Circuitry Sense amplifiers and address decoders Read Only memory (ROM) Single port , dual port memories Memory decoding SPICE Simulation

Analog Designing with Spice


Layout Designing
Manufacturing Process CMOS Process at a glance Metallization IC Fabrication Layout Design Rules Stick Diagrams Making layout from stick diagrams Euler Path Definition Layer Representation for CMOS n-Well process Design Rule Background Different Layout Designs Standard cell layout , Gate array layout Timing in layout Scribe lines Layer assignments Latchup in CMOS Internal , I/O Latchup Prevention techniques Technology Related CAD issues CMOS process layers Transistor Layout Vias and Contacts DRC Checker Dealing with interconnects Layout Validations , LVS